- #LATTICE SYNPLIFY PRO MF515 ERROR HOW TO#
- #LATTICE SYNPLIFY PRO MF515 ERROR FULL#
- #LATTICE SYNPLIFY PRO MF515 ERROR PRO#
- #LATTICE SYNPLIFY PRO MF515 ERROR CODE#
So this is how i arrived to hooking up a logic analyzer and seeing what is actually going on. And it resulted in consistent behavior on the FPGA between compile iteractions, but its consistently wrong behavior. I have found i can reduce the clock speed on one of the clocks (and updated the clock dividers/timers that run from that clock) and this got the timing analysis consistently in the green even if you mess with compiler settings. This particular problem i have narrowed down to the interaction of two state machines that run on different clocks (But at least divided down from the same clock source). Such as a timer implemented by comparing its 32bit value using >= operation and feeding the output of that straight on into other logic like state machines (no registering, just direct combinational out) Then there are things like 120bit wide FIFOs with a bunch of big MUXes hanging off them even tho it could have been a 9bit fifo and bus with a bit of smarts (Its all going out of a 500Kbit UART in the end, so super slow).
#LATTICE SYNPLIFY PRO MF515 ERROR CODE#
Looking trough the code i found some really long chains of logic. Went at it with the source code and i could get it to compile a more stable binary by massaging the compiler settings, but the timing analysis was not happy at all. I can't even do place and route on Lattice chips (It just does the synthesis step, the map place route export programming.etc is done by Lattices own tools) I assumed the logic is correct since it worked on real hardware, but once they kicked off production they got a significant amount of boards that didn't work. I can't seam to find the Synopsys Idenfity anywhere so guessing its not there, but im not surprised since the Lattice edition of Synplify is pretty cut down. But HOW does one do this in VHDL on Lattice Diamond + Synplify. I can do it in Altera tools easy, i can do it in Verilog easy. At this point i have been at it for hours and am finding it rather ridiculous how hard it is to just simply get a random burried signal out to a pin. Turns out Verilog hierarchical references only work on modules coded in Verilog. sv source file, connect it up into the VHDL top level file, and now just wire the.
#LATTICE SYNPLIFY PRO MF515 ERROR HOW TO#
And i get to work with a language i actually know how to use. Hierarchical references are also a pretty standard part of the feature set here in Verilog land so they do actually work in compilers. Turns out not everyone supports this 3) Fine i will do it in Verilog instead! SystemVerilog is supported. The compiler throws its arms up as soon as it gets to the "<<" part even tho it is in VHDL2008 mode and this is a VHDL2008 feature. 2) Do it in VHDL code: I barely even know any VHDL (I always used Verilog) but how hard can it be? Cool there is a thing called hierarchical references (just like in Verilog):Ĭode: val > Well. And that tool sucks anyway even when it does work (Altera SignalTap works way better).
#LATTICE SYNPLIFY PRO MF515 ERROR FULL#
It can only build a logic analyzer on the FPGA using memory blocks, but my FPGA is close to full already. bish bosh add a few signals to a list, compile it and away we go. 1) Just use a IDE tool: Altera has this nice tool in the IDE where you just add signals to a list and it then muxes this big list of signals out to a set of IO pins by JTAG commands. The juicy stuff is burred down in the hierarchy of submodules, so i needed a way to easily get one of those signals out to a IO pin.
#LATTICE SYNPLIFY PRO MF515 ERROR PRO#
Its running on a Lattice MachXO2 (And its pretty full too) with Symplify Pro in VHDL2008 So so after a bit of timing tweaking didn't fix it i decided to take a deeper look using a logic analyzer. It has some stability issues with it that need fixing and some of it is quite a mess. Unfortunately i had an old FPGA project from a guy who no longer works here dropped in my lap.